The present invention relates generally to memory sense amplifiers, and, more particularly, to a capacitively isolated mismatch compensated sense amplifier.
In dynamic random access memory (DRAM) devices, a sense amplifier is typically utilized to sense the voltage on a common bitline connected to each DRAM storage cell that comprises a storage capacitor and a transistor. The transistor selectively switches the stored capacitor voltage value onto the bitline when that cell is addressed during a read operation. The storage capacitor stores the relatively small voltage value that represents a logical binary “0” or “1” value. As semiconductor device technology continues to evolve towards providing smaller device sizes and more devices per integrated circuit (IC) (and thus smaller voltages utilized within the circuits within the IC), the inherent mismatch in the threshold voltage between the several transistors that typically comprise a sense amplifier becomes increasing difficult and important to properly compensate for.